MCF5206 & MCF5206E Microprocessor Support
- Full speed state analysis up to 33.33 MHz for MCF5206
- Full speed state analysis up to 54 MHz for MCF5206E
- Disassembly shows acquired data in the processor's instruction set mnemonics.
- Symbolically identifies all processor bus cycles
- Acquired data can be linked directly to HLL source files for source level debug
- 500 ps timing resolution enables detailed analysis of setup and hold times, edge-to-edge relationships, control timing, etc.
- All data acquired by the logic analyzer is time stamped to enable accurate time correlation of code execution to other system busses or hardware activity.
Separate probe adapters are available for either 3.3V or 5V operation.
Minimum System Requirements
- TLA7xx mainframe and one TLA7L3 acquisition module, 102 channels, 100 MHz state, 32K deep (200 MHz state, 136 channels and up to 64M deep available)
- Or TLA603 instrument, 102 channels, 100 MHz state, 32K deep (200 MHz state, 136 channels and up to 1M deep available)
- qty 3: P6434 high-density mictor probes
- TLA application software version 2.0 or greater
- Instrument setup software including clocking and channel assignments
- Symbol table of all bus cycle names
- Disassembler for MFC5206 and MFC5206E processors
- Hardware probe adapter
- User manual
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add probe adapter, please select one;
Last Modified: 1999-05-26 05:00:00